I. Field of the Disclosure
The technology of the disclosure relates generally to magnetic tunnel junctions (MTJs), and particularly to the use of MTJ bit cells in magnetic random access memory (MRAM), including two (2) transistor, two (2) MTJ (2T2MTJ) bit cells.
II. Background
Processor-based computer systems include memory for data storage. Memory systems are composed of resistive memory elements capable of storing data, wherein the form of the stored data depends on the type of memory employed. In particular, magnetic random access memory (MRAM) is an example of non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) of an MRAM bit cell. Data is stored in an MTJ as a magnetic state, wherein no electric current is required to preserve a stored data value. Thus, an MTJ can store data even when power is not supplied to the MTJ (i.e., the MTJ is non-volatile). Conversely, memory that stores data in the form of an electric charge, such as static random access memory (SRAM), requires power to preserve a stored data value (i.e., such memory is volatile). Thus, because an MTJ may store information even when power is turned off, particular circuits and systems may benefit from employing MRAM.
In this regard, FIG. 1 illustrates an exemplary MRAM bit cell 100 that includes a metal oxide semiconductor (MOS) (typically n-type MOS, i.e., NMOS) access transistor 102 integrated with an MTJ 104 for storing non-volatile data. The MRAM bit cell 100 may be provided in an MRAM memory used as memory storage for any type of system requiring electronic memory, such as a central processing unit (CPU) or processor-based system, as examples. The MTJ 104 includes a pinned layer 106 and a free layer 108 disposed on either side of a tunnel barrier 110 formed by a thin non-magnetic dielectric layer. When the magnetic orientation of the pinned layer 106 and the free layer 108 are anti-parallel (AP) to each other, a first memory state exists (e.g., a logical ‘1’). When the magnetic orientation of the pinned layer 106 and the free layer 108 are parallel (P) to each other, a second memory state exists (e.g., a logical ‘0’). Further, the access transistor 102 controls reading and writing of data to the MTJ 104. A drain (D) of the access transistor 102 is coupled to a bottom electrode 112 of the MTJ 104, which is coupled to the pinned layer 106. A word line 114 is coupled to a gate (G) of the access transistor 102. A source (S) of the access transistor 102 is coupled to a source line 116. A bit line 118 is coupled to a top electrode 120 of the MTJ 104, which is coupled to the free layer 108.
To read data stored in the MRAM bit cell 100, the resistance (R) of the MRAM bit cell 100 is measured. In particular, the word line 114 activates the access transistor 102 to allow current (I) to flow through the MTJ 104 between the bottom electrode 112 and the top electrode 120. The resistance (R) is measured by dividing a voltage (V) of the bit line 118 by the current (I) flowing between the bottom and top electrodes 112, 120. A lower resistance (R) is associated with a P orientation between the pinned layer 106 and the free layer 108. A higher resistance (R) is associated with an AP orientation between the pinned layer 106 and the free layer 108. Reading the MRAM bit cell 100 in this manner is not immediate, but rather such a read operation requires a certain amount of time to measure the resistance (R). As a non-limiting example, certain MRAM bit cells similar to the MRAM bit cell 100 require approximately five (5) nanoseconds (ns) of read sensing time to perform a read operation. However, certain circuits, such as a level two (L2) cache memory may require a faster read sensing time, such as three (3) ns, for example. Thus, it would be advantageous if MRAM bit cells could be provided that have a reduced read sensing time as compared to the MRAM bit cell 100 in FIG. 1.
In this regard, FIG. 2 illustrates an exemplary two (2) transistor, two (2) MTJ (2T2MTJ) bit cell 200. The 2T2MTJ bit cell 200 achieves a reduced read sensing time as compared to the read sensing time of the one (1) transistor MRAM bit cell 100 in FIG. 1. The 2T2MTJ bit cell 200 includes a first MTJ 202 and a second MTJ 204, wherein a first value stored in the first MTJ 202 is a complement of a second value stored in the second MTJ 204. A first bit line 206 is coupled to a free layer 208 of the first MTJ 202, and a drain (D) of a first access transistor 210 is coupled to a pinned layer 212 of the first MTJ 202. A tunnel barrier 213 is disposed between the free layer 208 and the pinned layer 212. A first source line 214 is coupled to a source (S) of the first access transistor 210. Similarly, a second bit line 216, which is a complement of the first bit line 206, is coupled to a free layer 218 of the second MTJ 204, and a drain (D) of a second access transistor 220 is coupled to a pinned layer 222 of the second MTJ 204. A tunnel bather 223 is disposed between the free layer 218 and the pinned layer 222. A second source line 224 is coupled to a source (S) of the second access transistor 220. A word line 226 is coupled to a gate (G) of the first access transistor 210 and a gate (G) of the second access transistor 220, wherein the first MTJ 202 and the second MTJ 204 are activated in response to the word line 226 transitioning to a logic high ‘1’ state.
With continuing reference to FIG. 2, to read the 2T2MTJ bit cell 200, the word line 226 activates the first and second access transistors 210, 220. A current (I) is generated that flows from the first source line 214 through the first MTJ 202 to the first bit line 206. A current (I) is also generated that flows from the second source line 224 through the second MTJ 204 to the second bit line 216. Rather than measuring the resistance (R) of the first MTJ 202 and the second MTJ 204 similar to reading the MRAM bit cell 100 in FIG. 1, the voltage (V) of the first MTJ 202 and the voltage (V) of the second MTJ 204 are evaluated by a sensing device, such as a differential operational amplifier (not shown). Such a sensing device determines the logical value stored in the first MTJ 202 based on the difference in voltages (V) of the first MTJ 202 and the second MTJ 204. Reading the 2T2MTJ bit cell 200 in this manner has a reduced read sensing time as compared to that of the MRAM bit cell 100 in FIG. 1. However, the additional circuit elements of the 2T2MTJ bit cell 200, such as the second bit line 216 and the second source line 224, may lead to more complex fabrication routing, and thus, higher parasitic resistance. Such higher parasitic resistance may limit the speed of the read sensing time of the 2T2MTJ bit cell 200. Therefore, it would be advantageous to achieve the reduced read sensing time of the 2T2MTJ bit cell 200 in FIG. 2 without being limited by a higher parasitic resistance.